1. Field of the Invention
The present invention relates to an electronic system including a semiconductor memory device and a method of refreshing the semiconductor memory device included in the electronic system.
2. Description of Related Art
In a conventional electronic system such as a memory board or a memory module including a plurality of dynamic semiconductor memory devices such as dynamic random access memory (DRAM), all the dynamic semiconductor memory devices included in the memory system are refreshed at the same time. Accordingly, there has been a problem that peak current is high during a refresh operation.
FIG. 1 is a block diagram of a memory system having a plurality of DRAMs in accordance with the conventional art. As shown in FIG. 1, the memory system includes a control device 10 and four slots M1, M2, M3, M4 each of which may receive a memory module.
Chip selection signals CSB1, CSB2, CSB3, CSB4 are applied to corresponding slots M1, M2, M3, M4, respectively. An inverted column address strobe signal CASB, an inverted row address strobe signal RASB and data DQ are applied to all of the slots M1, M2, M3, M4.
FIG. 2 illustrates how the signals are associated in the memory system of FIG. 1. The memory modules MM1, MM2, MM3, MM4 are received in corresponding slots M1, M2, M3, M4, (designated in FIG. 1) respectively. Each of the memory modules MM1, MM2, MM3, MM4 includes four DRAMs m1, m2, m3, m4 (although four is an exemplary number).
The DRAMs m1, m2, m3, m4 mounted on the memory module MM1 are connected in common to an inverted chip selection signal CSB1 as well as connected in common to the inverted column strobe signal CASB and the inverted row address strobe signal RASB. The data DQ1, DQ2, DQ3, DQ4 are applied to corresponding DRAMs m1, m2, m3, m4, respectively.
That is, the DRAMs m1, m2, m3, m4 in the same memory module are enabled in response to the same inverted chip selection signal of the inverted chip selection signals CSB1, CSB2, CSB3, CSB4 supplied from the control device 10. After the DRAMs m1, m2, m3, m4 are enabled, the data DQ1, DQ2, DQ3, DQ4 are transmitted thereto.
In general, during normal operation, an active command of the inverted row address strobe signal RASB is applied before a read/write command of the inverted column address strobe signal CASB is applied.
However, the read/write command of the inverted column address strobe signal CASB is applied to the system before the active command of the inverted row address strobe signal RASB to the memory system during a refresh operation. Accordingly, all the DRAMs m1-m4 in all the memory modules MM1-MM4 are refreshed at the same time. Therefore, peak current increases dramatically at this time.
FIG. 3 is a block diagram of internal circuits for performing the refresh operation in the system of FIG. 2. As shown in FIG. 3, the internal circuits include a memory cell array 20, a refresh enable signal generating circuit 22, a refresh counter 24 and a row address decoder 26.
The refresh enable signal generating circuit 22 detects when the inverted column address strobe signal CASB is applied before the inverted row address strobe signal RASB is applied and generates a refresh enable signal CBR.
The refresh counter 24 generates refresh address REFA in response to the refresh enable signal CBR. The row address decoder 26 generates word line selection signals WL1-WLk by decoding the refresh address REFA.
The memory cell array 20 is refreshed in response to the word line selection signals WL1-WLk. The word lines are selected in due order by the word line selection signals WL1-WLk, so that the memory cells connected to the word lines WL1-WLk are refreshed in word line selection order.
Japanese Patent Laid Open No. H11-134857 describes a solution to the problem that peak current increases during a refresh operation.
The conventional memory system of the Japanese Patent Laid Open No. H11-134857 discloses a memory system comprising a plurality of DRAMs and a decode chip having an address decoder for generating control signals to control the DRAMs. The decode chip further includes a refresh mode control circuit for determining a refresh mode based on control signals supplied from a microprocessor and generating a refresh control signal. The decode chip further includes a signal switching circuit for delaying in sequence control signals to be transmitted to the DRAMs when the refresh mode control circuit determines the refresh mode.
The conventional memory system determines the refresh mode in response to an inverted row address strobe signal RASB and an inverted column address strobe signal CASB. After determining the refresh mode, the conventional memory system generates a plurality of row address strobe signals to be applied to the corresponding DRAMs, respectively, in response to decoded signals generated by decoding address signals. Accordingly, the DRAMs in the memory system are refreshed in due order. However, in the conventional memory system, the refresh operation is controlled by the decode chip separately provided from the DRAMs, so that the configuration of the memory system is complicated.